Jungsook Yang

POWER to the people: A historyof chipmaking at IBM

Source : http://www.ibm.com/developerworks/power/library/pa-powerppl/?S_TACT=105AGX16&S_CMP=ART

Summary: In the last decade alone, IBM scientists have announced one semiconductor breakthrough after another: copper technology, silicon-on-insulator, silicon germanium, strained silicon, and low-k dielectrics. All of these technologies came out of IBM’s fertile in-house research community. This prowess in modern chipmaking know-how came out of the hermetically-sealed clean rooms of the most advanced R & D department in the semiconductor industry.

IBM’s 4 families of processors – the Power Architecture(TM), the PowerPC family of processors, the Star chips, power IBM mainframes have a common ancestor: the IBM 801. IBM CellBE has a Power-like PPU but the SPUs have completely different ISA.

IBM 801 : It started out attempting to solve the problem in the 1970s: switching telephone calls. The goal was to complete one instruction per clock cycle and accommodate 300 calls per minute. Most of the computers of the day had CISC instruction sets and the chip complexity became greater. IBM’s John Cocke sliced away at the redundancy in the instruction set and designed a machine with half the circuits of its contemporaries-that ran twice as fast as they did, known as RISC today. His work on RISC and optimizing compilers won him many awards including the 1987 Turing Award. IBM 801 never became a telephone switcher, instead it became the first RISC chip. The RISC architecture came to dominate the workstation and embedded markets.

POWER : POWER stands for Performance Optimization With Enhanced RISC. Descended directly from the 801 CPU, it is a 2nd-generation RISC processor.  801 was a very simple design. Because al instructions completed in one colck cycle, it lacked floating-point and superscalar (parallel processing) ability. The POWER architecture set out to correct this.

• POWER1 : released in 1990, 800,000 transistors per chip. functionally partitioned, superscalar, had separate floating-point registers and could scale from the low to the high end of the UNIX workstatios it was built for. The RSC implementation of the POWER1 microprocessor was used as the central processor for the Mars Pathfinder mission and is the chip from which the PowerPC line is descended.
• POWER2: released in 1993. 15 million transistors per chip. added a 2nd FPU and more cache. Powered the 32-node IBM DEEP BLUE(R) supercomputer that beat world champion Garry Kasparov at chess in 1997.
• POWER3 : released in 1998. 15 million transistors per chip. The first 64-bit symmetric multiprocessor (SMP). designed for scientific and technical computing apps. It had data prefetch engine, non-blocking interleaved data cache, dual floating point execution units, etc. POWER-II reimplemented POWER3 using copper interconnects, deliving double the performance at the same price.
• POWER4 : released in 2001. 174 millions transistors per processor. A gigaprocessor incorporating 0.18-micron copper and SOI (Silicon-on-Insulator) technology, the POWER4 was the single most powerful chip on the market when it was introduced. Each processor has 2 64-bit 1GHz+ PowerPC cores, making it the first server processor with a multicore design on a single die.
• POWER5 : released in 2003. 276 million transistors per processor. based on the 130-nanometer copper/SOI process, and featueres communication acceleration, chip multiprocessing, a larger L2 cche, a memory controller on the chip, simultaneous multithreading, advanced power management, eFuse (morphing) and hypervisor technology.

STAR power: PowerAS and RS64

PowerPC : PC stands for Performance Computing. introduced in 1993. open : it specifies an instruction set architecture that allows anyone to design and fabricate PowerPC-compatible processorsl and osurce code for software modules developed in support of PowerPC is freely available. The small size of the PowerPC core leaves a great deal of room on each die for additioal components, from added cache to coprocessors, allowing for an amazing amount of design flexibility.

CellBE : the newest member. 234 million transistors. It contains a Power Architecture-based control processor (PU) augmented with 8 SIMD Synergistic Processor Unit (SPU) and a rich set of DMA commands for efficient communications between them all.

Custom Chips : Nintendo GameCube’s Gekko, Cray’s X1 supercomputer chips, NVIDIA’s latest GeForce processor, and the MS Xbox and Sony playstatio use chip technology licensed from or manufactured by IBM. Various System-on-Chip designs are also based on Power Architecture technology.