Descriptions on my Current Projects
Networked Processor Array (NePA)
NePA is a multiprocessor platform with a 2D mesh topology Network-on-Chip (NoC) interconnect. NoC is implemented in SystemC and a synthesizable RTL model in Verilog HDL. OpenRISC instruction set simulator is used for processor simulation. I am researching on fast multicore architecture simulation, parallel algorithms development especially for graphics and DSP applications, and efficient scheduling and mapping techniques. The current publications regarding this project are listed in the following and more papers are expected to be published in the future.
- Seung Eun LEE and Nader Bagherzadeh, “A Variable Frequency Link for a Power-Aware Network-on-Chip (NoC), ” Integration, the VLSI Journal, Elsevier. 2009 (PDF)
- Seung Eun LEE and Nader Bagherzadeh, “A High-level Power Model for Network-on-Chip (NoC) Router, ” Computer & Electrical Engineering, Elsevier. 2009 (PDF)
- Seung Eun Lee and Nader Bagherzadeh, “Clock Boosting Router: Increasing the Performance of an Adaptive Router in Network-on-Chip (NoC)”, Scientia Iranica, Vol. 15, No. 6, pp. 579-588, December 2008.
- Wen-Hsiang Hu, Seugn Eun Lee, and Nader Bagherzadeh, “DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture”, NoCArc, First International Workshop on Network on Chip Architectures to be held in conjunction with MICRO-41, 2008. (PDF)
- Jun Ho Bahn and Nader Bagherzadeh, “A Generic Traffic Model for On-Chip Interconnection Networks”, NoCArc, First International Workshop on Network on Chip Architectures to be held in conjunction with MICRO-41, 2008. (PDF)
- Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn and Nader Bagherzadeh, “Self-optimized Routing in a Network-on-a-Chip,” 20th IFIP World Computer Congress, Milano, Italy 7-10 September 2008. (PDF)
- Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh, “Parallel FFT Algorithms on Network-on-Chips,” 5th International Conference on Information Technology : New Generations (ITNG 2008) (PDF)
- Nader Bagherzadeh and Masaru Matsuura, “Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip,” 5th International Conference on Information Technology : New Generations (ITNG 2008)
- Jun Ho Bahn, Nader Bagherzadeh, “Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip(NoC) Architecture,” 13th International CSI Computer Conference (CSICC 2008) (PDF)
- Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, and Nader Bagherzadeh, “A Generic Networ Interface Architecture for an NoC based Multiprocessor SoC,” International Symposium on Architecture of Computing System(ARCS2008), Lecture Notes in Computer Science, vol.4934, pp.247-260, Feb.2008. (PDF)
- Jun Ho Bahn, Seung Eun LEE, Yoon seok Yang, Jungsook Yang, and Nader Bagherzadeh, “Multi-Processor System Platform using Network-on-Chip (NoC) Techniques, ” appears in Parallel Processing Letters. (PDF)
- Jun-Ho Bahn, Seung Eun LEE, and Nader Bagherzadeh, “Design of a router for network-on-chip, ” International Journal of High Performance Systems Architecture 2007 – Vol. 1, No.2 pp. 98 – 105. (PDF)
- Seung Eun Lee, Jun Ho Bahn and Nader Bagherzadeh, “Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP),” Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), Oct. 2007 (PDF)
- Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, “Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture,”
in the Proc. of ITNG 2007.(PDF)
Parallel EFIE
Parallel processing using distributed computers becomes important as computationally demanding applications in electromagnetic fields require highly efficient yet cost effective solutions. We studied the development of parallel processing strategies of the Method of Moment applicable to a variety of electromagnetic problems such as scattering problems. A linear system of equations for the surface currents induced on a conducting scatterer is derived using the Method of Moment in conjunction with the RWG basis function. The Conjugate Gradient method is used to solve the linear equation. To reduce the total execution time of this procedure, we use distributed computers to process the most time consuming tasks, which
are building the Z matrix and finding the surface currents by the Conjugate Gradient method. Our parallelization scheme is tested and run up to 10 distributed computers and the Message Passing Interface (MPI) is used for communicating among the nodes.
- Haythem H. Abdullah, Jungsook Yang, Nader Bagherzadeh and Khalid F. Hussein, “Parallel Electric Field Integral Equation Solver for Arbitrary Shaped Conducting Bodies”, the 25th PIERS 2009 in Beijing, China (PDF)
